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Structural Reliability Analysis of
Interconnect Structures
for
Deep Sub-Micron Integrated Circuits, 18-9078
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Principal Investigators
Scott R. Runnels
Harry R. Millwater Jr.
Richard A. Page
Michael P. Enright
Inclusive Dates: 04/01/98 - Current
Background - The 1997 National Technology
Roadmap for Semiconductors (the Roadmap), prepared with input from over 200 industry
experts, is recognized as the most important document for guiding the industrys $20
billion/year world-wide R&D effort. As indicated in the Roadmap, building the
interconnecting metal lines on integrated circuit (IC) chips represents more than half of
the total manufacturing costs. The Roadmap correctly predicted that the industry would
migrate from aluminum- to copper-based interconnect lines. It also explained how new and
better dielectric materials would be introduced to insulate these interconnect lines from
each other. As these new materials are now being introduced and as the size of the
interconnects continues to shrink, their structural reliability has become one of the
industrys top technical concerns.
Approach - The objective of this project is to
provide a comprehensive and technically robust methodology for evaluating the structural
reliability of interconnect structures used in deep submicron ICs. Three of SwRIs
structural reliability analysis skills were adapted for this project, including 1) finite
element stress analysis (FEA), 2) probabilistic analysis, and 3) computer-vision-assisted
microscopy for deformation and failure analysis (DISMAP). During the first task of this
project, a representative interconnect structure was identified for study. The stress in
this representative structure was then simulated using an FEA model, which was then linked
to SwRIs probabilistic analysis software tool, NESSUS. Using NESSUS and
the FEA model, the effects of variations in the structures material properties and
process conditions on the likelihood of failure were quantified. The computational
approach was complemented by SwRIs unique and powerful DISMAP capability, in which
cross-sectioned integrated circuits are thermally loaded in a scanning electron
microscope. The images from before- and after-loading were processed by SwRIs
existing computer vision system to produce deformation and strain plots.
Accomplishments - During 1999, significant
technical results were produced. Recent results are shown in the top illustration, which
shows displacement vectors resulting from thermal cycling. The plot is produced by the
Institutes DISMAP technology and reveals, for the first time, the way submicron
interconnect structures interact with the surrounding dielectric field. The results show
previously unseen permanent structure deformation after the structure was heated to
deposition temperatures. They also reveal how material interfaces tend to slip during
heating. Similarly, as shown in the illustration on the bottom, this project has produced
probabilistic reliability estimates of interconnect structures. For the first time, the
relative importance of materials and process quality control are understood.

Displacement vectors produced on a Motorola chip sample
using the DISMAP technology identify possible failure modes due to thermal cycling.

This chart shows the relative importance of
statistical uncertainty on the probability of interconnect failure.
Materials Research and
Structural Mechanics Program
1999 IR&D Home SwRI Home
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