Development of a Very High-Speed, Mixed-Mode Time to Digital Application-Specific Integrated Circuit for Space Applications, 15-9163Printer Friendly Version
Inclusive Dates: 10/01/99 - Current
Background: Southwest Research Institute (SwRI) is internationally known for its expertise in space particle physics. SwRI has particle detectors in space on the New Millennium (PEPE) and CASSINI (CAPS) platforms. Earlier in 2000, SwRI's Imager for Magnetosphere to Aurora Global Exploration (IMAGE) launched, successfully placing the SwRI Medium Energy Neutral Atom (MENA) imager, along with five other instruments, in orbit around the Earth. SwRI is the prime contractor for IES and ALICE and is a subcontractor for ROSINA, all particle physics experiments for the European Space Agency's ROSETTA mission.
To maintain its state-of-the-art capability in space particle physics, SwRI is pursuing all aspects of instrument production and miniaturization. SwRI has concentrated on detector and ion optics design and, up to now, has not pushed technology in the area of high-speed data acquisition and mixed-mode Application-Specific Integrated Circuit (ASIC) design. The Time-to-Digital Converter (TDC) measures the time between pulses on a detector at a very high temporal resolution and is a key component of almost every particle physics instrument. The purpose of this project is to develop a monolithic mixed-mode ASIC to perform this task with a temporal resolution goal of 250 picoseconds.
Approach: The concept behind the Fast Data Acquisition Module (FDAM) is deceptively simple. The critical components are a delay line, several register arrays, a multiplexer, and a First in, First out (FIFO) buffer. A start pulse, either from a Time of Flight (TOF) instrument extractor pulse or a Microchannel Plate (MCP) triggers the beginning of the FDAM acquisition cycle. After a set delay, a pulse is provided to a multiple tap delay line that generates an output pulse on each tap, each delayed 250 picoseconds from the tap before it. Each tap is tied to the clock input of a D-flip/flop and effectively records the state of the input data at that moment in time. A high-speed comparator circuit creates input data for each row of D-flip/flops. Several banks of these D-flip/flops, each fed with a different high-speed comparator circuit allows spatial information to be extracted from the incoming pulses.
The team's approach to developing this concept is to use field-programmable gate arrays to implement the digital portion of the design and build the high-speed comparator circuitry from discrete components that correspond to Mixed-Mode ASIC elements. A custom test board holds all the components and provides input data pre-processing and interfaces to special test equipment. The results of this design and verification effort will eventually be ported to an ASIC that will use the same test bench.
Accomplishments: To date, the team has accomplished several key tasks. One significant effort was consulting with members of the scientific community to refine the requirements for such a device. Their input was crucial to the architectural development of the FDAM. The development board has been assembled (see illustration below), along with special test equipment and software, and is being evaluated in the laboratory. The digital portion, which is internal to the FPGA/ASIC, has been extensively simulated, and routing has been fine-tuned to achieve high temporal resolution. The high-speed analog comparators have been verified and tested. Thus far, the team has determined the concept is viable. Following the board evaluation, the team will port the design to the ASIC.