Structural Reliability Analysis of Interconnect
Structures for Deep
Inclusive Dates: 04/01/98 - 02/01/00
Background - On-chip interconnects are thin lines of metal that form the connecting circuitry in integrated circuits. These thin lines are embedded in an insulating material such as silicon dioxide and commonly occupy several layers above the underlying silicon substrate, in which the semiconductor devices reside. During the past ten years, the field of interconnect reliability analysis has matured. Nonetheless, because the problems associated with reliability continue to increase, still more advanced and robust methodologies for understanding and preventing interconnect failure are required.
Approach - Three key structural reliability analysis skills that are well established at SwRI were adapted for integrated circuit interconnect technology. These skills include finite element analysis, probabilistic analysis, and computer-vision-assisted strain mapping.
Accomplishments - Displacement vectors and strain contours were measured from a state-of-the-art chip using DISMAP. Strain contours concentrated at material interfaces reveal how inter-layer materials experience significant shearing and may contribute to delamination. Direct comparison of finite element modeling and DISMAP results reveals that modeling of single interconnects can capture local behavior but not the key large-scale shearing. The insight provided by DISMAP motivates the need for more robust modeling, especially of large-scale, three-dimensional effects and material interfaces.
NESSUS results, obtained using an elastic-plastic finite element model and some general assumptions regarding the statistical variation of the materials and process, show that the thermal expansion coefficient of the interconnect material (copper) dominates, meaning that testing and measurements should focus on issues relating to that factor at the expense of focusing on other factors whose variations have less impact.