Development of a Reusable CompactPCI to Local Bus Core, 15-9485Printer Friendly Version
Inclusive Dates: 07/01/04 - Current
Background - One of the flagship products of the Institute's spacecraft computers is the CompactPCI-based SC-9 computer. Programs such as Deep Impact, NPP, Orbital Express, NextView, and Kepler are examples of more than $28M in outside projects utilizing the SC-9 systems or its variants. The cornerstone of these systems is the CompactPCI (cPCI) bus interface. Interfacing a given module's resources to the cPCI bus is done through a cPCI to local bus bridge. The local bus is the internal module structure that interconnects various peripherals such as memory, analog to digital converters, and Field-Programmable Gate Arrays (FPGAs). Local bus architectures are traditionally a one-time unique interface with custom protocols for transferring the data to and from the cPCI bus. This one-time unique aspect represents significant nonrecurring engineering. To increase overall cost efficiencies and reduce system design time, this quick-look research project was undertaken to establish a reusable local bus architecture and corresponding logic for interfacing to the CompactPCI bus.
Approach - The first task in the development of a common cPCI to local bus interface is a detailed trade study of what interfaces will be supported on the local bus. This trade study will examine existing SwRI module designs, review upcoming program requirements, and create a baseline of the interfaces and protocols that will be supported on the local bus.
Following the establishment of the local bus architecture, a Verilog-based logic core will be designed to provide a common building block for future hardware modules. The logic core will provide a fully compliant CompactPCI interface and a local bus interface targeted at current flight-qualified FPGA technology. The verification of the core will occur through static timing, as well as the creation of a dynamic test bench. The test bench will actively exercise the core, monitor for protocol violations and logic faults, and simulate the peripherals that will make up the local bus. In addition to the logic core and test bench, an interface control drawing will be generated that will detail the requirements for interfacing to the core and resources provided by the cPCI to Local Bus Interface Core.
Accomplishments - The trade study has been completed and has resulted in a fully synchronous local bus design that includes arbitration and interface logic for Summit MIL-STD-1553 interfacing. The design and coding of the logic core have been completed, and the module is currently in simulation. Initial resource estimates indicate that it easily fits within existing radiation-hardened, space-qualified FPGA technology. A draft of the interface control drawing is in review.