Size, Weight, and Power Reduction
Using Application Specific Integrated
Circuit Technology in Electronics Systems:
A Multi-Division Presidential Discretion IR&D Initiative (Phase I), 16-R9608
Principal Investigators
Jennifer L. Alvarez
Charles W. Howard
Ronnie L. Killough
Andrew R. Moore
Inclusive Dates: 03/01/06 – 03/01/07
Background - Size, weight, and power consumption must be minimized in embedded systems. Often analog hardware, digital hardware, and software for embedded system designs must function within the limitations of off-the-shelf integrated circuits (ICs). This sometimes results in the use of additional ICs or in the use of only a portion of the available functionality within an IC increasing the size, weight, and power consumption of the product. Instead, it is advantageous to have a design that uses only the required hardware.
Approach - The purpose of this project is to develop SwRI capabilities to customize ICs for which off-the-shelf products are not available. The PDIR program involves four SwRI technical divisions. Although there is a different focus in each participating division, the primary goals and desired outcomes are beneficial to all. The overarching program objectives are to:
- Understand the engineering trade space among technology options in terms of functional performance, environmental tolerance, size, weight, power consumption, and cost.
- Understand the design flow, level of effort and resource requirements for developing solutions based on customized hardware, to include reconfigurable and non-reconfigurable customized computing systems and architectures.
- Obtain experience with representative techniques, technologies and tool sets by designing and specifying an application specific integrated circuit (ASIC).
- Establish at SwRI a sustainable ASIC design capability by capturing the process, resource and organizational expertise in a multi-division ASIC focus group.
Accomplishments - The objectives for the first phase of the project were to develop an understanding and gain experience in working with ASIC-related technology. A key benefit of this research is the ability to more fully respond to client inquires about the performance impacts, risks, development schedule, and costs of developing customized hardware at the IC level. Additionally, the investigation into the trade space for custom hardware provided new insights into the skills, tools, performance, technologies, and design approaches for customized hardware. An important result of this work was the definition of a design flow that fits within the Institute’s business model. The design flow defines the steps in the design process and identifies the activities and skills necessary to transition the design to an application-specific platform. The detailed investigation of the skills and tool investments required for these activities revealed the steps that require the development of in-house expertise and breakpoints in the flow that might provide advantages if outsourced.
