Measure Signal Performance Metrics on a Blade Processor Architecture, 16-R9668Printer Friendly Version
Inclusive Dates: 01/01/07 03/31/07
Background - Moore's Law states that the number of transistors that can be placed on a chip grows exponentially with respect to time. It has been observed that the number of transistors doubles every two years. Because it has been three years since the first FRONTIER wideband systems were deployed, this project was to determine how much Moore’s Law would allow the system size, weight, and power (SWaP) to be reduced by using available server technology.
Approach - The scope of the original investigation was limited to measuring the performance of two software routines that account for the greatest amount of CPU loading, and then extrapolating these numbers to determine the required system size for a complete system. The preliminary results showed that moving the software channelizer from a 1U dual AMD Opteron processor to a 1U Intel quad core Xeon could reduce the number of servers by a factor of four while reducing power by an equivalent amount. Additionally it was found that the throughput of this change in architecture increased by a factor of almost two. The second software application is the signal processing suite that originally ran on a rack containing 88 Intel P4s, and this subsystem could be duplicated using two 7U blade servers each having 10 blades with dual quad-core XEONs with a space savings of 28U drawing 50 percent of the original power.
The scope of the original investigation was expanded to build a prototypical system to convert from a 32-bit build environment to a 64-bit build, and also to evaluate the performance of the Intel optimizing compiler instead of the usual gcc compiler.
Accomplishments - The original FRONTIER system was contained in two 19-inch racks and consumed 14KVa of power, while the new system is housed in a single 19-inch rack drawing just under 8KVa. Additionally, system throughput was increased by a factor of eight. The conversion from a 32-bit to a 64-bit build was straightforward and allowed the system RAM to be doubled to increase system delay from 40 seconds to more than one minute. Using the Intel compiler showed an average increase in CPU utilization by an average 25 percent.