Size, Weight, and Power Reduction Using ASIC Technology in Electronics Systems: A Multi-Division Presidential Discretion IR&D Initiative (Phase II), 16-R9762

Principal Investigators
Jennifer L. Alvarez
Ronnie L. Killough
Martin Dennis
Buddy Walls

Inclusive Dates:  10/01/07 – Current

Background - Size, weight, and power consumption must be minimized in embedded systems. Often, analog hardware, digital hardware, and software for embedded system designs must function within the limitations of off-the-shelf integrated circuits (ICs). This sometimes results in the use of additional ICs or in the use of only a portion of the available functionality within an IC increasing the size, weight and power consumption of the product. Instead, it is advantageous to have a design that uses only the required hardware. Application-specific integrated circuits (ASICs) have the potential of performing with the best trades among size, weight, and power consumption over commercially available ICs.

Approach - The purpose of this project is to develop SwRI capabilities to customize ICs for which off-the-shelf products are not available. The project involves four SwRI technical divisions. Although there is a different focus in each participating division, the primary goals and desired outcomes of the project are beneficial to all. The objectives are to:

• Understand the engineering trade space among technology options in terms of functional performance, environmental tolerance, size, weight, power consumption, and cost.
   
• Understand the design flow, level of effort and resource requirements for developing solutions based on customized hardware, to include reconfigurable and non-reconfigurable customized computing systems and architectures.
   
• Obtain experience with representative techniques, technologies and tool sets by designing and specifying an ASIC.
   
• Establish at SwRI a sustainable ASIC design capability by capturing the process, resource and organizational expertise in a multi-division ASIC focus group.

Accomplishments - The objectives for this phase of the project were to further SwRI's capabilities in the development of technology related to ASICs by conducting design activities toward ASIC fabrication. Work in customized IC development has progressed in a number of parallel efforts including design and implementation of signal-processing algorithms in a hardware description language, completing a design that will be implemented in a radiation-hardened ASIC, performing design and layout of analog circuit components for an ASIC implementation, and developing tools to aid in the allocation of functions to hardware elements. Experience gained in these areas will enable SwRI to evaluate ASIC approaches and where appropriate, offer ASIC design solutions that meet or exceed the client expectations for performance, environmental tolerance, size, weight, power consumption and cost in embedded electronic systems for both space and terrestrial applications.

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