Risk Mitigation of the SIDECAR™ ASIC System Interface in Focal Plane Array
Inclusive Dates: 07/12/10 – Current
Background - The SIDECAR™ (system image, digitizing, enhancing, controlling, and retrieving) ASIC (application-specific integrated circuit) device is a compact, low-power solution for focal plane array applications. The interface to the SIDECAR ASIC represents a current general design challenge for space system electronics, which is handling an increase in performance while reducing power and maintaining reliability. The current system electronic design architecture cannot handle the maximum data output from the SIDECAR ASIC and will lead to data loss.
Approach - The main purpose of this project is to improve the design architecture of SwRI's space system electronics. A trade study was initiated to evaluate possible solutions to accommodate the demanding performance requirements of the SIDECAR ASIC. Key parameters within the trade study were performance (power, speed, and complexity), expandability and radiation hardness. The results of the trade study showed that two field programmable gate arrays (FPGA) technologies were capable of meeting the basic interface needs of the SIDECAR ASIC and were selected for further evaluation. FPGA code was developed and implemented in the two selected FPGA devices, and the board design architecture was developed for both devices.
Accomplishments - The first FPGA evaluated has lower power consumption and requires fewer components, which generates lower board power consumption. However, the first FPGA barely meets the speed requirements, with only 12 percent of the available logic utilized. The second FPGA evaluated meets the speed requirement with adequate margin while using 9 percent of the available logic. The second FPGA consumes more power and requires more components so the overall board power consumption is higher. The estimated power difference between the two board designs is approximately 700mW. The FPGA and the voltage regulator supplying the FPGA core voltage accounts for the majority of the power difference. A board will be built with the second FPGA because it can meet the performance requirements of the SIDECAR ASIC. The second FPGA also has more capabilities should the investigators decide to add more functionality to the board design. The prototype board that will be built will be used in an upcoming demonstration. It will also allow for further familiarization with the SIDECAR ASIC interface and provide a platform to improve the overall performance of the system electronics.