Preliminary Design of a PCI / VME Bridge Chip, 15-9172Printer Friendly Version
Inclusive Dates: 10/01/99 - 06/30/00
Background - Recent years have seen the beginning of a migration of space command and data-handling systems from the VERAmodule Eurocard (VME) bus to the CompactPCI (cPCI) bus. Spurred by the inclusion of the cPCI bus in the new NASA Jet Propulsion Laboratory (JPL) x2000 architecture, cPCI offers the promise of increased bandwidth and performance for space missions. The migration of spaceflight-proven VME systems, including SwRI's own SC-9 family of spacecraft computers, to the cPCI bus introduces substantial risk and schedule impact, as well as substantial NRE costs. SwRI has addressed this migration with the development of a PCI to VME Bridge chip (PVB), providing for direct inclusion of flight heritage VME systems with cPCI systems. The PVB provides the core-enabling technology to an architecture combining new, high-performance cPCI modules, with heritage space-qualified VME modules. The PVB design has received overwhelming response from industry, and has been directly responsible for $8 million of new contracts, as well as significantly expanding industry presence and customer base. This presidential discretionary project contained phase one of the PVB development.
Approach - The goals of this project were to conduct a trade study with industry to determine the market requirements for a new PCI / VME Bridge, develop a specification for the chip, as well as conduct initial prototyping to determine design complexity and resource requirements. This phase of the development serves as a baseline for the subsequent migration of the initial prototype PVB to a space-qualified application specific integrated circuit (ASIC).
Accomplishments - The conclusions of the SwRI trade study indicate that, at a minimum, the PVB should provide translation between the PCI Target to VME Master interface, as well as translation between the PCI Initiator to VME Slave interface. Additionally, the bridge should provide the capabilities to serve as a slot 1 controller on the VME bus, as well as providing interrupt forwarding from the VME bus to the cPCI bus.
Initial prototyping of the PVB was performed to determine design complexity and resource requirements. Several industry partners expressed concerns that the resources required for the PVB would push the design into a large-capacity ASIC, thus increasing design risk and reducing time to market. The PVB was successfully synthesized into a standard Actel A54SX72 Field Programmable Gate Array (FPGA), using approximately 73 percent of the available resources. These results confirm the feasibility of the design and provide the framework for the final design and ASIC migration.