Development of a PCI / VME Bridge ASIC, 15-9204Printer Friendly Version
Inclusive Dates: 04/01/00 - 04/01/01
Background - Recent years have seen the beginning of a migration of space command and data-handling systems from the VERAmodule Eurocard (VME) bus to the CompactPCI (cPCI) bus. Spurred by the inclusion of the cPCI bus in the new NASA Jet Propulsion Laboratory (JPL) x2000 architecture, cPCI offers the promise of increased bandwidth and performance for space missions. The migration of spaceflight-proven VME systems, including SwRI’s own SC-9 family of spacecraft computers, to the cPCI bus introduces substantial risk and schedule impact, as well as substantial NRE costs. SwRI has addressed this migration with the development of a PCI to VME Bridge chip (PVB), providing for direct inclusion of flight heritage VME systems with cPCI systems. The PVB provides the core-enabling technology to an architecture combining new, high-performance cPCI modules, with heritage space-qualified VME modules. The PVB design has received overwhelming response from industry, and has been directly responsible for $8 million of new contracts, as well as significantly expanding industry presence and customer base. This presidential discretionary project contained phase one of the PVB development.
Approach - The conclusion of phase one of the PCI to VME bridge development resulted in the establishment of the feasibility of the design as well as providing an initial design baseline. The goals of this project were to complete the design of the PCI to VME Bridge, develop an automated design test bench and produce an electrical test fixture for evaluation of the actual bridge hardware. The final design will be released to an ASIC vendor for migration to a space-qualified application specific-integrated circuit (ASIC).
Accomplishments - Discussions with our industry partners revised our initial discussions by focusing development efforts on the bridge interfacing external PCI Initiators to external VME targets. Detailed specifications, as well as test procedures were created for the new bridge design. The design was completed, simulated, and prototyped in an Actel A54SX72 and Actel A54SX32 Field Programmable Gate Arrays (FPGA). The results validate the operation of the bridge at the full 33MHz for the PCI bus, as well as providing a full VME slot 1 controller, and interrupt handler.
A self-contained, integrated test bench was also developed for the design and will serve as the primary verification tool once the design is migrated to an ASIC. Hardware testing of the design was accomplished through the creation of a custom electronics board providing interconnect logic and prototyping resources for the bridge. Extensive software support was developed to support the electrical checkout of the bridge.
A draft teaming agreement with an ASIC vendor is currently under evaluation. The ASIC vendor has received a FPGA programming file for used on their flight processor cards. Finally, this presidential IR&D has resulted in the presentation of three formal papers at various conferences, as well as numerous discussions with industry on the availability of the bridge.