Applied Research into Space Data Networks Using the SpaceWire Protocol, 15-9472

Principal Investigators
Buddy Walls
Sandra Dykes
Mark Johnson

Inclusive Dates:  04/01/04 - Current

Background - During the last 25 years, the Institute has made a substantial commitment to the development of advanced computer systems for space. SwRI's internal research programs have been a major element of this commitment, supporting the development of key technologies to compete for tomorrow's space missions. One emerging technology area is the creation of a Local Area Network (LAN) as the backbone for intra-spacecraft communications. A core technology for this infrastructure is a high-performance, high-reliability physical and data communication layer. Recently, the European Space Agency (ESA) has standardized a high-speed serial bus called SpaceWire for this specific application. This research program investigates the applicability of SpaceWire as a network backbone, and the logistics of hosting Internet Protocols (IP) to SpaceWire. Additionally, this program will create a prototype SpaceWire Interface Module (SLIM) for use as a test bed and as a building block spacecraft computer avionics.

Approach - The research program was separated into two distinct components. One component focused on research into the feasibility and applicability of IP over SpaceWire, while the other component performed the hardware design of the SLIM. The research component will investigate the required IP stack interface to Spacewire, various IP operational scenarios, onboard network architectures, and define how the IP layer will be implemented onto of the SpaceWire protocol layers. An important aspect of the research will be ensuring that the architecture defined to support IP can still accommodate normal SpaceWire packet traffic.

The initial hardware design phase is closely coupled with the research component in the creation of the final hardware architecture. Following this initial trade study, the hardware design phase will be broken into five major components, including establishment of a detailed requirements specification, creation of a baseline module design, implementation of board architecture, parts procurement, and fabrication and verification of the module. The final deliverables for the hardware phase are a completed and verified SpaceWire module, along with a reusable Verilog logic core capable of being used in future SpaceWire designs.

Accomplishments - The initial research component has been completed. An architecture has been defined and the software protocols established for interfacing IP, and in particular an IP stack to the SpaceWire module. The research component is currently being expanded to look at automatic address routing and its applicability to SpaceWire. The hardware component is still ongoing, with four of the five phases completed. The only hardware task remaining is the fabrication and verification of the module. All requirements definition, design, and procurement phases have been completed.

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