Miniaturized SIGINT System, 16-R9773Printer Friendly Version
Inclusive Dates: 12/19/07 Current
Background - The goal of this project is to reduce the size, weight and power (SWaP) requirements of signal intelligence (SIGINT) systems. The project is in the last phase of a four-phase approach that methodically determines the optimal platforms and technologies and adapts known algorithms for the selected miniaturized system, while researching and implementing new processes that meet customers' emerging requirements.
All phases have been joint efforts between two SwRI technical research divisions. These divisions have both independent and shared project goals. The goals are to develop a portable wideband V/UHF SIGINT system that provides a wideband DF capability and to implement a complete SIGINT system capable of detecting, channelizing, and demodulating multiple target signals over a 30 MHz bandwidth. Phase 1 focused on the embedded design. Phase 2 focused on the implementation and optimization of the Phase 1 design on commercial-off-the-shelf (COTS) development boards. Phase 3 developed a field-operational SIGINT system prototype to convince prospective clients that SwRI has developed a viable man-transportable V/UHF DF system and to avoid the perception of vaporware. Phase 4 goals are to expand the existing Phase 3 SIGINT system capability to include wideband scanning detection and DF in a further reduced SWaP form factor, and to detect and classify wireless communications.
Approach - Both divisions are targeting COTS development boardsets with field-programmable gate array (FPGA) technology to achieve a reduced SWaP system and are focused on porting existing algorithms from PC servers to FPGAs.
Accomplishments - To date, SwRI has created a field system prototype for V/UHF operations. The FPGA-based prototype is 30 pounds and 50 watts, compared with 175 pounds and 2,100 watts of legacy PC-based systems. The prototype provides automatic and manual DF and geolocation. Also, SwRI has implemented a 90 MHz channelizer-based demodulator that processes up to 64 signals in parallel and fits in a low-power Xilinx Spartan device.