A method and system is provided for improved access to flash memory devices. A system may include a control state module configured to receive memory access commands. The system may further include a plurality of operation sequencer modules configured to execute a pipeline schedule for the performance of the received memory access commands. The pipeline schedule may be configured to enable parallel execution of the memory access commands among a plurality of flash dies of the flash memory. Each of the operation sequencers is associated with one or more of the flash dies.
US Patent and Trademark Office
Michael A. Koets; Larry T. McDaniel III; Miles R. Darnell