Mitigating Risk for a Highly Scalable/Highly Configurable Solid State Recorder for
Multi-Mission Space Applications, 15-R8158

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Principal Investigator
Charles W. Howard

Inclusive Dates:  06/14/10 – 10/29/10

Background - The core technical problem is to provide a standard platform for multiple applications with system flexibility through configuration, so that providers can consolidate payload interface and SSR functionality with a single electronics module.

Approach - This project has been crucial to clearly defining the trade space between ingest, storage and playback bandwidth, SSR size and architectural flexibility. The multi-mission mass memory (M4) is the baseline architecture resulting from the evaluation of risks and mission requirements across multiple programs; a system approach was taken to bound the trade space and specify a single platform to satisfy many applications and needs, such as image ingest or science data storage.

The M4 architecture is based upon an interface-rich, rad-hard field programmable gate array (FPGA), allowing architectural flexibility through functional configuration of the FPGA logic. The M4 FPGA will support a set of core capabilities that can be configured through software settings after power on, as well as offering alternate capabilities through additional FPGA NRE. Because the platform is feature-rich, few applications would require module NRE. The project's focus has been on the effect of scaling ingest and playback ports and data rates, maximum bandwidth, and additional functions the platform can support. A great deal of effort has been placed on ensuring architectural flexibility at build-time, rather than on run-time configuration options. The M4 is based on heritage components and circuits, and incorporates mitigation techniques suitable for a radiation intense environment, thus positioning the M4 at a credible Technical Readiness Level.

Accomplishments - Evaluating the system trades prompted developing a bandwidth versus power calculator (BVP). The M4 architecture offers multiple memory banks, which are defined to provide optimum memory bandwidth through interleaving access to n devices in a multi-chip module and take advantage of the block-based nature of flash. The BVP tool takes into account the board I/O, active memory banks and memory controller performance when deriving the memory bandwidth and access characteristics, which, in turn, drives the power calculation. A valid power estimate is an important marketing element because of the embedded power requirements for a satellite.

A commercial prototyping platform was derived to mimic the M4 topology, offering immediate opportunity to retire program risk and develop user-specific capabilities. This model will provide a working prototype to support future study of M4 functions such as I/O rate, protocols, memory bandwidth, file management and downlink formatting. An additional benefit is that such low-cost prototypes can be used as for marketing purposes, system modeling and software development. Two customers are committed to a purchase of the M4 prototyping capability, leading to future purchase of flight-quality M4-based products.

The M4 platform can satisfy the needs of SwRI's customer base looking to consolidate the payload and SSR functionality into a standard electronics module by supporting core capabilities and offering configurable features to fulfill unique mission requirements. SwRI can pursue additional performance and system flexibility with the M4 prototype, and maintain claim on the intellectual property derived from this project.


Figure 1. 3U Multi-Mission Mass Memory Prototyping Platform


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