Background
Within the past few years SwRI has successfully entered new markets in applications involving high data rate (giga bits per second, or Gbps) signal processing and data management. New market opportunities center on the demand for sophisticated, high performance signal processing systems for small spacecraft. The levels of complexity and performance required by these new applications significantly exceeds SwRI’s current heritage with space-based signal processing systems. The emergence of new commercial space-qualified components has changed both the scope of what is practical for these applications and the approaches best suited to the implementation of these systems.
Approach
The investigation explores the use of modern, high-speed digital to analog and analog to digital converters and the latest space-hardened field programmable gate arrays (FPGAs). These components are essential to many of the target applications. Recently developed converters provide extremely high sample rates (measured in billions of samples per second). Interfacing to these new converters presents fundamental new challenges both in the analog electronics associated with the converters and in the management of digital data streams. The feasibility of a novel FPGA-based interface architecture to support the high throughput of these convertors is modeled and analyzed. The architecture is realized as new prototype hardware that serves as a true measurement of performance and a proving ground for tailored high-speed processing algorithms.
Accomplishments
Two novel architectures passed through the modeling and analysis phase. The first is named SERDES CML to LVDS (SCL). The second is named after the high-speed interface protocol JESD204B. Limitations of the SCL architecture were characterized and the architecture is feasible. The robustness of the JESD204B architecture proved to be the dominate architecture. Analysis shows that meeting a throughput of 38.4 Gbps is feasible. Prototype hardware is designed and fabricated. The JESD204B highspeed interface is demonstrated. The design and demonstration are documented in the final report submitted October 1, 2018. The final report also documents many details of high-speed digital interface printed circuit board design that will be utilized in ongoing space applications targeting data rates in the tens of Gbps.